1. Field of the Invention
This invention relates to field effect transistor devices. In particular it relates to reducing the failure rate of such devices.
2. Description of the Prior Art
In recent years the field effect transistor (FET) has progressed from limited utility to a full-scale product technology. At the present time, numerous memory and logic systems utilize this technology. The technological advantages inherent in FET's, such as low power and high-packaging density, have made large scale integration (LSI) a reality. In fact, the FET is rapidly replacing the bipolar transistor as the preferred technology for LSI systems.
When any new technology is implemented, new methods of manufacture often have to be developed; and the reliability of these processes and the resulting product must be assured. Unlike the bipolar transistor, the FET is a surface device and is sensitive to a different set of processing variables, e.g., charge control and gate insulator integrity.
One type of FET which has shown great promise is the metal-oxide-semiconductor field effect transistor (MOSFET) which utilizes a composite gate dielectric of silicon dioxide-phosphosilicate glass. The advantages of such a composite gate dielectric have been described by Miller and Barson in U.S. Pat. No. 3,343,059, assigned to the same assignee as the present invention. FET's utilizing silicon dioxide alone as the gate dielectric experience undesirable shifts in one or more of their operating characteristics or qualities at medium and high operating temperatures when operated under their usual bias conditions for extended periods of time. In the ambient environment of the systems in which these devices are used, e.g., data processing storage systems, such shifts are unacceptable. In general, devices exhibiting these shifts must be rejected as unsuitable. Because many hundreds or thousands of such devices are today formed in the same semiconductor substrate, the cost of even a single reject may be quite substantial. The alternatives open to the manufacturing engineer are to reject the entire chip or wafer or to probe the device, isolate the defective devices and insure that they are not used in an operating environment. Either alternative is quite expensive and has delayed or completely halted the introduction of improved semiconductor devices.
In the above described patent, Miller and Barson arrived at a solution to the parameter shift problem which significantly advanced the art. They found that the use of a vitreous film of a mixture of silicon oxide and phosphorus pentoxide (P.sub.2 O.sub.5) substantially improved the electrical qualities of the field effect transistor devices.
Although the physics of the improvement achieved by adding phosphosilicate glass was not fully understood by Miller and Barson at the time of filing their application, more recently it has been shown that phosphosilicate glass (PSG) is particularly effective in reducing the rate of degradation of threshold voltage due to positive ion contamination drift, thought to be sodium (Na.sup.+). The trapping mechanism of a PSG film is believed to be a coulombic attraction between a non-bridging oxygen ion (O.sup.-) and the mobile contamination ion (Na.sup.+).
It has been found that the thicker the layer of PSG, and the greater the mole percent of P.sub.2 O.sub.5 it contains, the more stable will be the device. (The PSG acts as a contaminant trap.) On the other hand, too thick a layer leads to PSG polarization shifts of undesirable proportions. Too little PSG doesn't trap enough contaminants to assure reliability.
For example, we have found that production lots of 512 bit memory array chips, each containing about 4000 gates consisting of 600 A SiO.sub.2 and 100 A PSG gate insulation, exhibited an unexpectedly high number of failures. The failures fall into two principal categories: (1) gate shorts and (2) severe threshold voltage (V.sub.T) shifts. A gate short is a breakdown of the thin gate insulator which is electrically characterized as a catastrophic, permanent failure under stress.
The V.sub.T shift ( .DELTA.V.sub.T) caused a N channel enhancement mode device to operate in the depletion mode. In other words, a normally "off" device becomes normally "on". The shift was detected on chips which were stressed under standard "worst case" conditions for relatively short times, i.e., a gate voltage of around 11 volts at 130.degree. C. ambient temperature for 100 hours. The failing units exhibit no change in input leakage or general threshold degradation, indicating that the failures are not inherent in the FET technology.